Journey from Single-core Acceleration to Multi-core Heterogeneous Systems Jain, Vikram. creator author. aut http://id.loc.gov/vocabulary/relators/aut Verhelst, Marian. author. aut http://id.loc.gov/vocabulary/relators/aut SpringerLink (Online service) text sz 2024 1st ed. 2024. monographic eng

electronic

electronic resource

access XXIII, 186 p. 93 illus., 83 illus. in color. online resource. This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning. . Chapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion. by Vikram Jain, Marian Verhelst. Electronic circuits Embedded computer systems Machine learning Microprocessors Computer architecture Electronic Circuits and Systems Embedded Systems Machine Learning Processor Architectures TK7867-7867.5 9783031382307 https://doi.org/10.1007/978-3-031-38230-7 https://doi.org/10.1007/978-3-031-38230-7 230915 20251030110815.0 978-3-031-38230-7