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    <title>Understanding Logic Locking</title>
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    <namePart>Zamiri Azar, Kimia.</namePart>
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    <namePart>Mardani Kamali, Hadi.</namePart>
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    <namePart>Farahmandi, Farimah.</namePart>
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    <namePart>Tehranipoor, Mark.</namePart>
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    <dateIssued encoding="marc">2024</dateIssued>
    <edition>1st ed. 2024.</edition>
    <issuance>monographic</issuance>
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    <extent>XVI, 381 p. 1 illus. online resource.</extent>
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  <abstract>This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO’s and DON’Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking. Covers modern VLSI design, testability and debug, and hardware security threats at different levels of abstraction; Provides a comprehensive overview of logic locking techniques and their applications to hardware security; Covers logic locking from implementation to evaluation, different assumptions, models and abstraction layers.</abstract>
  <tableOfContents>Basics of VLSI Design -- Basics of VLSI Testing and Debug -- IP Protection in VLSI Design: A Historical View -- Making a Case for Logic Locking -- Fundamentals of Logic Locking -- Infrastructure around Logic Locking -- Impact of Satisfiability Solvers on Logic Locking -- Post-Satisfiability Era: Countermeasures and Threats -- Design-for-Testability and its Impact on Logic Locking -- Emergence of Cutting-edge Technologies on Logic Locking -- Logic Locking in Future IC Supply Chain Environments -- Multilayer Approach to Logic Locking -- A Step-by-Step Guide for Protecting/Locking Your IP -- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.</tableOfContents>
  <note type="statement of responsibility">by Kimia Zamiri Azar, Hadi Mardani Kamali, Farimah Farahmandi, Mark Tehranipoor.</note>
  <subject authority="lcsh">
    <topic>Electronic circuit design</topic>
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  <subject authority="lcsh">
    <topic>Embedded computer systems</topic>
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  <subject authority="lcsh">
    <topic>Electronic circuits</topic>
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  <subject>
    <topic>Electronics Design and Verification</topic>
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  <subject>
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  <subject>
    <topic>Electronic Circuits and Systems</topic>
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  <identifier type="isbn">9783031379895</identifier>
  <identifier type="uri">https://doi.org/10.1007/978-3-031-37989-5</identifier>
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