03970nam a22005775i 4500 978-981-97-3477-1 DE-He213 20251030112708.0 cr nn 008mamaa 240802s2024 si | s |||| 0|eng d 9789819734771 978-981-97-3477-1 10.1007/978-981-97-3477-1 doi TK7800-8360 TJF bicssc TEC008000 bisacsh TJF thema Yue, Jinshan. author. aut http://id.loc.gov/vocabulary/relators/aut 81840 High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture [electronic resource] / by Jinshan Yue. 1st ed. 2024. Singapore : Springer Nature Singapore : Imprint: Springer, 2024. XVI, 118 p. 81 illus., 78 illus. in color. online resource. text txt rdacontent computer c rdamedia online resource cr rdacarrier text file PDF rda Springer Theses, Recognizing Outstanding Ph.D. Research, 2190-5061 Introduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect. Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices. . Electronics. 65899 Electronic circuits. Microprocessors. 59300 Computer architecture. Computational intelligence. 64052 Electronics and Microelectronics, Instrumentation. 65902 Electronic Circuits and Systems. Processor Architectures. Computational Intelligence. 64052 SpringerLink (Online service) Springer Nature eBook Printed edition: 9789819734764 Printed edition: 9789819734788 Printed edition: 9789819734795 Springer Theses, Recognizing Outstanding Ph.D. Research, 2190-5061 66370 https://doi.org/10.1007/978-981-97-3477-1 ZDB-2-ENG ZDB-2-SXE 62200 62200