03783nam a22005295i 4500001001800000003000900018005001700027007001500044008004100059020003700100024003500137050001600172072001600188072002300204072001500227100008200242245015300324250001800477264007200495300006500567336002600632337002600658338003600684347002400720490007200744505042500816520136401241650002402605650002502629650002802654650002702682650003902709650006202748650003702810650002902847650003902876710003402915773002602949776003602975776003603011776003603047830007903083856004603162912001403208912001403222999001703236978-981-97-3477-1DE-He21320251030112708.0cr nn 008mamaa240802s2024    si |    s    |||| 0|eng d  a97898197347719978-981-97-3477-17 a10.1007/978-981-97-3477-12doi 4aTK7800-8360 7aTJF2bicssc 7aTEC0080002bisacsh 7aTJF2thema1 aYue, Jinshan.eauthor.4aut4http://id.loc.gov/vocabulary/relators/aut98184010aHigh Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architectureh[electronic resource] /cby Jinshan Yue.  a1st ed. 2024. 1aSingapore :bSpringer Nature Singapore :bImprint: Springer,c2024.  aXVI, 118 p. 81 illus., 78 illus. in color.bonline resource.  atextbtxt2rdacontent  acomputerbc2rdamedia  aonline resourcebcr2rdacarrier  atext filebPDF2rda1 aSpringer Theses, Recognizing Outstanding Ph.D. Research,x2190-50610 aIntroduction -- Basis and research status of neural network processor -- Neural network processor for specific kernel optimized data reuse -- Neural network processor with frequency domain compression algorithm optimization -- Neural network processor combining digital and computing in memory architecture -- Digital computing in memory neural network processor supporting large scale models -- Conclusion and prospect.  aNeural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies. For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time. This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices. . 0aElectronics.965899 0aElectronic circuits. 0aMicroprocessors.959300 0aComputer architecture. 0aComputational intelligence.96405214aElectronics and Microelectronics, Instrumentation.96590224aElectronic Circuits and Systems.24aProcessor Architectures.24aComputational Intelligence.9640522 aSpringerLink (Online service)0 tSpringer Nature eBook08iPrinted edition:z978981973476408iPrinted edition:z978981973478808iPrinted edition:z9789819734795 0aSpringer Theses, Recognizing Outstanding Ph.D. Research,x2190-506196637040uhttps://doi.org/10.1007/978-981-97-3477-1  aZDB-2-ENG  aZDB-2-SXE  c62200d62200