04075nam a22004094u 4500 10.1002/9781394171910 Wiley 20251030120311.0 cr nn 008mam|a 231013t2023||||xxu fs| |0|| 0|eng|| 9781394171910 electronic 10.1002/9781394171910 doi eng Munir, Arslan aut 91761 Accelerators for Convolutional Neural Networks [electronic resource] Arslan Munir, Joonho Kong, Mahmood Azhar Qureshi 1 Wiley 2023 Wiley 2023 304pp.; text txt rdacontent computer c rdamedia online resource cr rdacarrier text file rdaft PDF Accelerators for Convolutional Neural Networks Comprehensive and thorough resource exploring different types of convolutional neural networks and complementary accelerators Accelerators for Convolutional Neural Networks provides basic deep learning knowledge and instructive content to build up convolutional neural network (CNN) accelerators for the Internet of things (IoT) and edge computing practitioners, elucidating compressive coding for CNNs, presenting a two-step lossless input feature maps compression method, discussing arithmetic coding -based lossless weights compression method and the design of an associated decoding method, describing contemporary sparse CNNs that consider sparsity in both weights and activation maps, and discussing hardware/software co-design and co-scheduling techniques that can lead to better optimization and utilization of the available hardware resources for CNN acceleration. The first part of the book provides an overview of CNNs along with the composition and parameters of different contemporary CNN models. Later chapters focus on compressive coding for CNNs and the design of dense CNN accelerators. The book also provides directions for future research and development for CNN accelerators. Other sample topics covered in Accelerators for Convolutional Neural Networks include: How to apply arithmetic coding and decoding with range scaling for lossless weight compression for 5-bit CNN weights to deploy CNNs in extremely resource-constrained systems State-of-the-art research surrounding dense CNN accelerators, which are mostly based on systolic arrays or parallel multiply-accumulate (MAC) arrays iMAC dense CNN accelerator, which combines image-to-column (im2col) and general matrix multiplication (GEMM) hardware acceleration Multi-threaded, low-cost, log-based processing element (PE) core, instances of which are stacked in a spatial grid to engender NeuroMAX dense accelerator Sparse-PE, a multi-threaded and flexible CNN PE core that exploits sparsity in both weights and activation maps, instances of which can be stacked in a spatial grid for engendering sparse CNN accelerators For researchers in AI, computer vision, computer architecture, and embedded systems, along with graduate and senior undergraduate students in related programs of study, Accelerators for Convolutional Neural Networks is an essential resource to understanding the many facets of the subject and relevant applications. Neural Networks 91501 Artificial Intelligence 58441 Embedded Systems & Smart Cards 91584 CNN acceleration; CNN prototyping; hardware accelerators; compressive coding; dense CNNs; sparse CNNs; HW/SW co-design; HW/SW co-scheduling Kong, Joonho aut 91762 Qureshi, Mahmood Azhar aut 91763 Printed edition: 9781394171880 https://doi.org/10.1002/9781394171910 Wiley Online Library https://onlinelibrary.wiley.com/action/showBook?doi=10.1002%2F9781394171910 Wiley Online Library Cover Image https://onlinelibrary.wiley.com/cms/asset/caa9b508-248c-44e5-a05b-de65d73eb0d8/9781394171910.cover.gif Wiley Online Library 67079 67079