basic technology of artificial intelligence basic technology of artificial intelligence Khanna, Vinod Kumar 1952- creator author. Institute of Physics (Great Britain) publisher. text bibliography enk 2024 monographic eng access 1 online resource (various pagings) : illustrations (some color). The revolutionary impact of advances in artificial intelligence on consumer and industrial electronics has significantly increased the demand for specialized processing units for AI workloads. AI-Processor Electronics: Basic technology of artificial intelligence explores the principles and technology behind these processors, which perform fast, energy-efficient data processing and complex computations. The book begins with an overview of AI, machine learning, and deep learning, and a brief introduction to digital computer electronics. It highlights the limitations of traditional CPUs in modern AI, discussing parallel computing and AI-optimized hardware that are specially tailored and adapted to meet AI requirements. The book then covers various AI processors, including graphical, tensor, neural, convolutional neural network, vision, sparse neural network, graph analytics, associative memory, and quantum processing units. 1. Artificial intelligence, machine learning, deep learning and generative artificial intelligence -- 1.1. Introduction -- 1.2. AI versus ML vs DL vs Gen AI -- 1.3. Ethics of AI -- 1.4. Types of machine learning -- 1.5. Artificial neural networks -- 1.6. AI computing -- 1.7. Aims, scope and organization of the book -- 1.8. Summary and the way forward 2. Computing electronics fundamentals -- 2.1. Introduction -- 2.2. Electronic signals and related terms -- 2.3. Binary numbers and Boolean algebra -- 2.4. Binary logic -- 2.4.4 Basic logic gates -- 2.5. Metal-oxide semiconductor field-effect transistor and related technologies -- 2.6. CMOS-based NOT gate and universal logic gates -- 2.7. Realization of all the logic gates from universal gates -- 2.8. Flip-flops made with NAND gates -- 2.9. Binary addition -- 2.10. Binary subtraction -- 2.11. Binary multiplication -- 2.12. Binary division -- 2.13. Summary and the way forward 3. Central processing unit, and the von Neumann bottleneck -- 3.1. Introduction -- 3.2. The conventional computing workhorse -- 3.3. Basic units inside the CPU -- 3.4. The processing core -- 3.5. Components of the CPU -- 3.6. CPU cache, and the computer memory hierarchy -- 3.7. Computer architecture -- 3.8. von Neumann or Princeton architecture -- 3.9. RISC and CISC processors -- 3.10. Multi-core CPU operation on MIMD architecture -- 3.11. Threading, multithreading and hyperthreading in a CPU -- 3.12. Usage scenario of CPUs in AI -- 3.13. CPU for AI or ML work -- 3.14. Acceleration technologies in CPUs -- 3.15. Harward architecture -- 3.16. Summary and the way forward 4. Parallel computing architecture -- 4.1. Introduction -- 4.2. Flynn's classification of computer organization by the number of simultaneously manipulated instructions/data items -- 4.3. Challenges of AI computing, and their encumbrance on the processor of a computer -- 4.4. Parallel computing -- 4.5. Types of parallelism -- 4.6. Parallelism in software engineering -- 4.7. Parallel processors -- 4.8. Summary and the way forward 5. Optimized AI-computing within physical limits of transistors -- 5.1. Introduction -- 5.2. Downscaling limits of chip dimensions, and evolution of domain-specific architecture -- 5.3. Domain-specific hardware accelerators -- 5.4. AI-optimized hardware -- 5.5. Techniques of deep learning model compression -- 5.6. Sparsity enforcement in deep learning -- 5.7. Data compression for saving storage space and memory bandwidth -- 5.8. Zero-skipping method -- 5.9. Low-precision calculations -- 5.10. Faster memory access -- 5.11. Summary and the way forward 6. Graphical processing unit -- 6.1. Introduction -- 6.2. The GPU evolution -- 6.3. GPU launching -- 6.4. CUDA program structure -- 6.5. CUDA program flow -- 6.6. Thread, thread block and grid hierarchy -- 6.7. Hardware perspective -- 6.8. Fermi architecture -- 6.9. Thread-block and warp scheduling -- 6.10. Role of GPUs in AI context -- 6.11. GPU examples -- 6.12. Summary and the way forward 7. Tensor processing unit -- 7.1. Introduction -- 7.2. Tensor, TensorFlow and tensor processing unit -- 7.3. Chronological history and features of TPU -- 7.4. Specialties of TPUs for AI work -- 7.5. Driving factors for motivation for TPU -- 7.6. The structural units and instruction set of TPU -- 7.7. TPU operation -- 7.8. Summary and the way forward 8. Neural processing unit -- 8.1. Introduction -- 8.2. Approximation as a means of computation efficiency enhancement -- 8.3. Conversion of general-purpose code into neural representation -- 8.4. Parts of NPU -- 8.5. Processing engine -- 8.6. NPU operation -- 8.7. NPU performance -- 8.8. NPU as a hardwired multilayered perceptron neural network -- 8.9. AXNet accelerator -- 8.10. RENO : a reconfigurable accelerator -- 8.11. The DianNao family of energy-efficient hardware accelerators -- 8.12. The Ascend AI processor -- 8.13. Further NPU chip examples -- 8.14. Summary and the way forward 9. Convolution neural network processor, and the vision processing unit -- 9.1. Introduction -- 9.2. Convolution neural network -- 9.3. Constituent layers of a CNN -- 9.4. CNN accelerator -- 9.5. Eyeriss CNN accelerator -- 9.6. Vision processing unit -- 9.7. Commercial VPU performance capabilities -- 9.8. Summary and the way forward 10. Compressed and sparse neural network processors -- 10.1. Introduction -- 10.2. Sparsity in neural networks -- 10.3. Acceleration of 2:4 fine-grained sparsity pattern -- 10.4. Energy-efficient inference engine (EIE) by deep compression -- 10.5. Sparse convolution neural network (SCNN) accelerator -- 10.6. Sparse neural accelerator processor (SNAP) -- 10.7. The SNAP system -- 10.8. Summary and the way forward 11. Graph analytics processor for graph algorithm computations -- 11.1. Introduction -- 11.2. Graph and graph algorithm -- 11.3. Overcoming the difficulties encountered in processing graph algorithms -- 11.4. Structural dissection, and understanding the distinctive features of graph processor architecture -- 11.5. Exclusively developed modules of the graph processor -- 11.6. Fabrication of specimen graph processor device and evaluation of its operation -- 11.7. GraphCore intelligence processing unit -- 11.8. Intel's PIUMA architecture processor -- 11.9. Summary and the way forward 12. Associative processing unit -- 12.1. Introduction -- 12.2. Adopting a data-centric computing strategy to cope with the von Neumann bottleneck -- 12.3. Content addressable memory -- 12.4. Construction of a generic AiMP -- 12.5. Operation cycles of AiMP -- 12.6. Performing the AND operation on an AiMP -- 12.7. Arithmetic operations on AiMP -- 12.8. In-memory processor for big data analysis -- 12.9. Summary and the way forward 13. Quantum computing principles and devices -- 13.1. Introduction -- 13.2. Peregrination from classical to quantum computing -- 13.3. Concise recapitulation of quantum mechanics -- 13.4. Qubits and their properties -- 13.5. Quantum computing devices -- 13.6. Summary and the way forward 14. Quantum logic gates and circuits -- 14.1. Introduction -- 14.2. Quantum logic gates -- 14.3. Quantum circuits -- 14.4. Quantum Fourier transform (QFT) as a primary tool for performing arithmetic operations on a quantum computer -- 14.5. QFT adder for numbers encoded in n qubits -- 14.6. QFT multiplier -- 14.7. Summary and the way forward 15. Quantum processing unit -- 15.1. Introduction -- 15.2. Quantum random-access memory (QRAM) -- 15.3. Layered architecture of a quantum computer -- 15.4. Organization of a superconducting quantum computer -- 15.5. Summary and the way forward. (i) As a reference book for undergraduate and graduate engineers, and PhD students to keep abreast with the recent advances. (ii) As a technology update for scientists and engineers working on research and development of AI hardware. specialized Vinod Kumar Khanna. "Version: 20250101"--Title page verso. Includes bibliographical references. Full-text restricted to subscribers or individual document purchasers. Also available in print. Mode of access: World Wide Web. System requirements: Adobe Acrobat Reader, EPUB reader, or Kindle reader. Vinod Kumar Khanna, PhD (Physics), is an independent researcher at Chandigarh, India; a former emeritus scientist, Council of Scientific and Industrial Research (CSIR), India, and Emeritus Professor, Academy of Scientific and Innovative Research (AcSIR), Ghaziabad, India; a retired chief scientist, CSIR-Central Electronics Engineering Research Institute, Pilani, India and professor, AcSIR, India. He has worked for more than 37 years on the design, fabrication, and characterization of power semiconductor devices, MEMS, and nanotechnology-based sensors. He has published 194 research papers in refereed journals and conference proceedings, 21 books, and six chapters in edited books. He has five patents to his credit, two US and three Indian. Microprocessors Artificial intelligence Parallel processing (Electronic computers) Quantum computing Electronic devices & materials TECHNOLOGY & ENGINEERING / Electronics / General TK7895.M5 K533 2024eb Release 24 2024 collection 9780750362597 9780750362580 https://iopscience.iop.org/book/mono/978-0-7503-6259-7 https://iopscience.iop.org/book/mono/978-0-7503-6259-7 Full-text restricted to subscribers or individual document purchasers. CaBNVSL 250203 20251030124835.0 9780750362597 eng