| 000 | 03918nam a22005655i 4500 | ||
|---|---|---|---|
| 001 | 978-3-031-38230-7 | ||
| 003 | DE-He213 | ||
| 005 | 20251030110815.0 | ||
| 007 | cr nn 008mamaa | ||
| 008 | 230915s2024 sz | s |||| 0|eng d | ||
| 020 |
_a9783031382307 _9978-3-031-38230-7 |
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| 024 | 7 |
_a10.1007/978-3-031-38230-7 _2doi |
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| 050 | 4 | _aTK7867-7867.5 | |
| 072 | 7 |
_aTJFC _2bicssc |
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| 072 | 7 |
_aTEC008010 _2bisacsh |
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| 072 | 7 |
_aTJFC _2thema |
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| 100 | 1 |
_aJain, Vikram. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _966036 |
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| 245 | 1 | 0 |
_aTowards Heterogeneous Multi-core Systems-on-Chip for Edge Machine Learning _h[electronic resource] : _bJourney from Single-core Acceleration to Multi-core Heterogeneous Systems / _cby Vikram Jain, Marian Verhelst. |
| 250 | _a1st ed. 2024. | ||
| 264 | 1 |
_aCham : _bSpringer Nature Switzerland : _bImprint: Springer, _c2024. |
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| 300 |
_aXXIII, 186 p. 93 illus., 83 illus. in color. _bonline resource. |
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| 336 |
_atext _btxt _2rdacontent |
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| 337 |
_acomputer _bc _2rdamedia |
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| 338 |
_aonline resource _bcr _2rdacarrier |
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| 347 |
_atext file _bPDF _2rda |
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| 505 | 0 | _aChapter 1: Introduction -- Chapter 2 Algorithmic Background for Machine Learning -- Chapter 3 Scoping the Landscape of (Extreme) Edge Machine Learning Processors -- Chapter 4 Hardware-Software Co-optimization through Design Space Exploration -- Chapter 5 Energy Efficient Single-core Hardware Acceleration -- Chapter 6 TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip -- Chapter 7 DIANA: Digital and ANAlog Heterogeneous Multi-core System-on-Chip -- Chapter 8 Networks-on-chip to Enable Large-scale Multi-core ML Acceleration -- Chapter 9 Conclusion. | |
| 520 | _aThis book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations. Discusses the need for scaling to multi-core systems for machine learning and several architectural and software optimizations; Covers single-core, homogeneous and heterogeneous multi-core Systems-on-chip for machine learning applications; Discusses the benefits of heterogeneity in the context of machine learning. . | ||
| 650 | 0 |
_aElectronic circuits. _965535 |
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| 650 | 0 |
_aEmbedded computer systems. _964625 |
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| 650 | 0 |
_aMachine learning. _955059 |
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| 650 | 0 |
_aMicroprocessors. _959300 |
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| 650 | 0 |
_aComputer architecture. _966037 |
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| 650 | 1 | 4 |
_aElectronic Circuits and Systems. _965536 |
| 650 | 2 | 4 |
_aEmbedded Systems. _966038 |
| 650 | 2 | 4 |
_aMachine Learning. _955059 |
| 650 | 2 | 4 |
_aProcessor Architectures. _966039 |
| 700 | 1 |
_aVerhelst, Marian. _eauthor. _4aut _4http://id.loc.gov/vocabulary/relators/aut _966040 |
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| 710 | 2 | _aSpringerLink (Online service) | |
| 773 | 0 | _tSpringer Nature eBook | |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031382291 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031382314 |
| 776 | 0 | 8 |
_iPrinted edition: _z9783031382321 |
| 856 | 4 | 0 | _uhttps://doi.org/10.1007/978-3-031-38230-7 |
| 912 | _aZDB-2-ENG | ||
| 912 | _aZDB-2-SXE | ||
| 999 |
_c56286 _d56286 |
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