000 04573cam a2200505 i 4500
001 9781003187080
003 FlBoTFG
005 20251030122229.0
006 m o d
007 cr cnu|||unuuu
008 241029s2025 flu eo 000 0 eng d
040 _aOCoLC-P
_beng
_erda
_epn
_cOCoLC-P
020 _a9781003187080
_q(electronic bk.)
020 _a1003187080
_q(electronic bk.)
020 _a9781040133514
_q(electronic bk. : EPUB)
020 _a1040133517
_q(electronic bk. : EPUB)
020 _z9781032033921
020 _z9781032030791
020 _a9781040133484
_q(electronic bk. : PDF)
020 _a1040133487
_q(electronic bk. : PDF)
024 7 _a10.1201/9781003187080
_2doi
035 _a(OCoLC)1464076152
035 _a(OCoLC-P)1464076152
050 4 _aTK7874
072 7 _aTEC
_x007000
_2bisacsh
072 7 _aTJFC
_2bicssc
100 1 _aYang, Xiaokun,
_eauthor.
_992936
245 1 0 _aIntegrated Circuit Design :
_bIC Design Flow and Project-Based Learning /
_cXiaokun Yang.
250 _aFirst edition.
264 1 _aBoca Raton :
_bCRC Press,
_c2025.
300 _a1 online resource (xlii, 464 pages).
336 _atext
_btxt
_2rdacontent
337 _acomputer
_bc
_2rdamedia
338 _aonline resource
_bcr
_2rdacarrier
505 0 _aChapter 1- Introduction to IC DesignChapter 2- IC Design FlowChapter 3- Introduction to Verilog HDLChapter 4- RTL Design with Verilog HDLChapter 5- Design Simulation with Verilog HDLChapter 6- Synthesis: Matching Verilog HDL with Basic Combinational and Sequential CircuitsChapter 7- FSM DesignChapter 8- FSM-Datapath Design and Bus CommunicationChapter 9- Numerical Hardware Design and IntegrationChapter 10- Streaming and Iterative Design on Numerical HardwareChapter 11- Timing Constraints and High-Speed RTL DesignChapter 12- SoC Design and Integration
520 _aThis textbook seeks to foster a deep understanding of the field by introducing the industry integrated circuit (IC) design flow and offering tape-out or pseudo tape-out projects for hands-on practice, facilitating project-based learning (PBL) experiences. Integrated Circuit Design: IC Design Flow and Project-Based Learning aims to equip readers for entry-level roles as IC designers in the industry and as hardware design researchers in academia. The book commences with an overview of the industry IC design flow, with a primary focus on register-transfer level (RTL) design, the automation of simulation and verification, and system-on-chip (SoC) integration. To build connections between RTL design and physical hardware, FPGA (field-programmable gate array) synthesis and implementation is utilized to illustrate the hardware description and performance evaluation. The second objective of this book is to provide readers with practical, hands-on experience through tape-out or pseudo tape-out experiments, labs, and projects. These activities are centered on coding format, industry design rules (synthesizable Verilog designs, clock domain crossing, etc.), and commonly-used bus protocols (arbitration, handshaking, etc.), as well as established design methodologies for widely-adopted hardware components, including counters, timers, finite state machines (FSMs), I2C, single/dual-port and ping-pong buffers/register files, FIFOs, floating-point units (FPUs), numerical hardware (Fourier transform, matrix-matrix multiplication, etc.), direct memory access (DMA), image processing designs, neural networks, and more. The textbook caters to a diverse readership, including junior and senior undergraduate students, as well as graduate students pursuing degrees in electrical engineering, computer engineering, computer science, and related fields. The target audience is expected to have a basic understanding of Boolean Algebra and Karnaugh Maps, as well as prior familiarity with digital logic components such as AND/OR gates, latches, and flip-flops. The book will also be useful for entry-level RTL designers and verification engineers who are embarking on their journey in application-specific IC (ASIC) and FPGA design industry.
588 _aOCLC-licensed vendor bibliographic record.
650 0 _aIntegrated circuits.
_959299
650 7 _aTECHNOLOGY / Electricity
_2bisacsh
_992937
856 4 0 _3Taylor & Francis
_uhttps://www.taylorfrancis.com/books/9781003187080
856 4 2 _3OCLC metadata license agreement
_uhttp://www.oclc.org/content/dam/oclc/forms/terms/vbrl-201703.pdf
942 _cE-Books
999 _c67428
_d67428