Chapter 1- Introduction to IC DesignChapter 2- IC Design FlowChapter 3- Introduction to Verilog HDLChapter 4- RTL Design with Verilog HDLChapter 5- Design Simulation with Verilog HDLChapter 6- Synthesis: Matching Verilog HDL with Basic Combinational and Sequential CircuitsChapter 7- FSM DesignChapter 8- FSM-Datapath Design and Bus CommunicationChapter 9- Numerical Hardware Design and IntegrationChapter 10- Streaming and Iterative Design on Numerical HardwareChapter 11- Timing Constraints and High-Speed RTL DesignChapter 12- SoC Design and Integration

This textbook seeks to foster a deep understanding of the field by introducing the industry integrated circuit (IC) design flow and offering tape-out or pseudo tape-out projects for hands-on practice, facilitating project-based learning (PBL) experiences. Integrated Circuit Design: IC Design Flow and Project-Based Learning aims to equip readers for entry-level roles as IC designers in the industry and as hardware design researchers in academia. The book commences with an overview of the industry IC design flow, with a primary focus on register-transfer level (RTL) design, the automation of simulation and verification, and system-on-chip (SoC) integration. To build connections between RTL design and physical hardware, FPGA (field-programmable gate array) synthesis and implementation is utilized to illustrate the hardware description and performance evaluation. The second objective of this book is to provide readers with practical, hands-on experience through tape-out or pseudo tape-out experiments, labs, and projects. These activities are centered on coding format, industry design rules (synthesizable Verilog designs, clock domain crossing, etc.), and commonly-used bus protocols (arbitration, handshaking, etc.), as well as established design methodologies for widely-adopted hardware components, including counters, timers, finite state machines (FSMs), I2C, single/dual-port and ping-pong buffers/register files, FIFOs, floating-point units (FPUs), numerical hardware (Fourier transform, matrix-matrix multiplication, etc.), direct memory access (DMA), image processing designs, neural networks, and more. The textbook caters to a diverse readership, including junior and senior undergraduate students, as well as graduate students pursuing degrees in electrical engineering, computer engineering, computer science, and related fields. The target audience is expected to have a basic understanding of Boolean Algebra and Karnaugh Maps, as well as prior familiarity with digital logic components such as AND/OR gates, latches, and flip-flops. The book will also be useful for entry-level RTL designers and verification engineers who are embarking on their journey in application-specific IC (ASIC) and FPGA design industry.

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